In synchronous digital systems, a clock signal serves as the time reference around which data is driven in the circuit. Within the circuit, clocked state elements, such as flip-flops, registers, and latches, often store data that correspond to a particular state. As a result, clock signals and other input data to these elements should conform to certain timing requirements to ensure proper function in the circuit.
Clock skew, or differences in the propagation delays of the various paths in a clock tree, represents a significant timing consideration that clock distribution techniques seek to improve. When clock skew is not controlled below tolerable levels, the clock signal arrives at state elements at unmanageably different points in time, causing incorrect state values to become stored in state elements. This may occur, for example, when the clock skew occupies too significant a portion of the clock period. This situation is of particular concern as clock frequencies grow increasingly faster.
A known clock tree design technique attempts to control clock skew by ensuring that logic gates in each level of a tree, such as clock buffers (which are often inserted along a path to maintain sharper clock edges) have the same size. Another design technique equalizes the number of logic gates in all paths from source to state element.
These conventional methods, however, do not address a major source of clock skew caused by different types of logic gates being disposed within the same levels in a clock tree. This source of clock skew is a side-effect of conventional clock distribution techniques, which often involve complex clock trees that include different types of logic gates within the same level. Such techniques include clock buffering (i.e., disposing buffer gates in a clock tree to create sharper clock edges) and clock gating (i.e., disposing logic gates in a clock tree to allow one or more inactive modules in a digital system to be disabled to save power). Because different types of gates generally introduce differing amounts of propagation delay, they may create increased clock skew effects. Consequently, current methods such as matching buffers size and equalizing the number of gates in a path do not adequately control clock skew below tolerable limits.
Accordingly, there remains a need for an improved method of reducing clock skew that addresses the clock skew created by different types of logic gates being disposed within the same level of a clock tree.